In addition to boundary scan applications, Altera devices use the JTAG port for other applications, such as device configuration and on‑chip debugging features available in the Quartus II software.The bank of DRs is the primary data path of the JTAG circuitry.The figure below illustrates the boundary-scan testing concept.
The figure below shows a typical application in a design with multiple instances of the IP core.
The hub automatically arbitrates between multiple applications that share a single JTAG resource.
The JTAG protocol alleviates the need for physical access to IC pins via a shift register chain placed near the I/O ring.
This set of registers near the I/O ring, also known as boundary scan cells (BSCs), samples and forces values out onto the I/O pins.
The tool set consists of a set of GUIs, IP core intellectual property (IP) cores, and Tcl application programming interfaces (APIs).
The GUIs provide the configuration of test signals and the visualization of data captured during debugging.
This test data forces a known pattern to the pins connected to the affected BSCs.
If the adjacent IC at the other end of the PCB trace is JTAG‑compliant, the BSC of the adjacent IC samples the test pattern and feeds the BSCs back to the software for analysis.
The Tcl scripting interface provides automation during runtime.